There are many types of transistors all of whose particular shape and composition are chosen for the type of operation the transistor is to perform. Many transistors have silicon nitride (or just "nitride") layers therein. For example, a simple n-channel transistor is formed of a semiconductor substrate, a dielectric and a conductive layer over the dielectric layer. The dielectric layer is typically formed of three layers, a silicon oxide (or just "oxide") layer on the substrate, a nitride layer over the oxide layer and an oxide layer covering the nitride layer. This type of dielectric is known as an ONO (oxide-nitride-oxide) dielectric.
ONO can be found in other types of transistors. They are common in erasable programmable read only memory (EPROM) cells, electrically erasable programmable read only memory (EEPROM) cells and in nitride read only memory (NROM) cells. In the latter, the cell is formed of the ONO layer on the substrate with a polysilicon layer over the ONO layer.
The process of creating a cell is shown in FIGS. 1A, 1B and 1C, to which reference is now made. The ONO layers 10, 12 and 14 must be laid down on the p-type silicon substrate 16 and then cut (or etched) to the desired size and shape. The etching is produced by first patterning a layer of photoresist 18 on top of the ONO layer in the places where the ONO is desired. An etch operation is then performed, to remove the upper oxide and nitride layers 14 and 12, respectively, but the etch affects only the places where there is no photoresist. The output of the etch operation is a substrate with cells 20 of ONO.
As shown in FIG. 1B, an implant operation occurs (shown by arrows 30) which implants ions, such as Arsenic or Phosphorous, into the areas between the cells 20. This creates n-type source and/or drain areas 32 (FIG. 1 B) for the memory array cells in the p-type silicon substrate 16. If the source and/or drain areas are formed into lines, as is common for EPROM, EEPROM and NROM arrays, they are called the "diffusion bit lines" or "bit lines". The term "diffusion area" will be used to refer to sources and drains and the term "bit line" will be used throughout to describe diffusion bit lines and diffusion areas not yet formed into bit lines.
The photoresist 18 is removed, after which a thick bit line oxide 24 is then grown (FIG. 1C) between neighboring cells 20 to protect bit lines 32 and to electrically isolate neighboring cells 20 from each other.
It is also known to implant the bit lines 32 through the ONO layers 10, 12 and 14 after patterning with photoresist 18. The ONO layers 10, 12 and 14 are then etched, to remove the relevant sections of nitride layer 12, the photoresist 18 is removed and bit line oxide 24 is grown. Without the removal of nitride layer 12, bit line oxide 24 cannot be grown since the presence of nitride prevents oxidation.
The plasma etch is not a clean operation and, if enough contamination is left on the substrate 16 or on the side walls of the ONO, then the cell performance is degraded. Furthermore, the etching operation is not exact and, often, the etch can penetrate the substrate 16. This can ruin the electrical operation of the affected cell.